Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/656077
Title: A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
Authors: Supreet Jeloka;Naveen Bharathwaj Akesh;Dennis Sylvester;David Blaauw
subject: SRAM|configurable memory|reconfigurable sense amplifier|content addressable memory (CAM)|Computation-in-memory
Year: 2016
Publisher: IEEE
Abstract: Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.
URI: http://localhost/handle/Hannan/160438
http://localhost/handle/Hannan/656077
ISSN: 0018-9200
1558-173X
volume: 51
issue: 4
Appears in Collections:2016

Files in This Item:
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7400984.pdf3.26 MBAdobe PDFThumbnail
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Title: A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
Authors: Supreet Jeloka;Naveen Bharathwaj Akesh;Dennis Sylvester;David Blaauw
subject: SRAM|configurable memory|reconfigurable sense amplifier|content addressable memory (CAM)|Computation-in-memory
Year: 2016
Publisher: IEEE
Abstract: Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.
URI: http://localhost/handle/Hannan/160438
http://localhost/handle/Hannan/656077
ISSN: 0018-9200
1558-173X
volume: 51
issue: 4
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7400984.pdf3.26 MBAdobe PDFThumbnail
Preview File
Title: A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
Authors: Supreet Jeloka;Naveen Bharathwaj Akesh;Dennis Sylvester;David Blaauw
subject: SRAM|configurable memory|reconfigurable sense amplifier|content addressable memory (CAM)|Computation-in-memory
Year: 2016
Publisher: IEEE
Abstract: Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.
URI: http://localhost/handle/Hannan/160438
http://localhost/handle/Hannan/656077
ISSN: 0018-9200
1558-173X
volume: 51
issue: 4
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7400984.pdf3.26 MBAdobe PDFThumbnail
Preview File