Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/647210
Title: The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET
Authors: Wen-Kuan Yeh;Wenqi Zhang;Yi-Lin Yang;An-Ni Dai;Kehuey Wu;Tung-Huan Chou;Cheng-Li Lin;Kwang-Jow Gan;Chia-Hung Shih;Po-Ying Chen
subject: FinFET|width quantization|reliability
Year: 2016
Publisher: IEEE
Abstract: In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (W<sub>Fin_bottom</sub>), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner W<sub>Fin_bottom</sub> device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner W<sub>Fin_bottom</sub> device shows more serious degradation on drain current (I<sub>D</sub>) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker W<sub>Fin_bottom</sub> device shows almost insensitively degradation with the variation of stressing voltage.
URI: http://localhost/handle/Hannan/179622
http://localhost/handle/Hannan/647210
ISSN: 1530-4388
1558-2574
volume: 16
issue: 4
Appears in Collections:2016

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Title: The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET
Authors: Wen-Kuan Yeh;Wenqi Zhang;Yi-Lin Yang;An-Ni Dai;Kehuey Wu;Tung-Huan Chou;Cheng-Li Lin;Kwang-Jow Gan;Chia-Hung Shih;Po-Ying Chen
subject: FinFET|width quantization|reliability
Year: 2016
Publisher: IEEE
Abstract: In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (W<sub>Fin_bottom</sub>), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner W<sub>Fin_bottom</sub> device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner W<sub>Fin_bottom</sub> device shows more serious degradation on drain current (I<sub>D</sub>) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker W<sub>Fin_bottom</sub> device shows almost insensitively degradation with the variation of stressing voltage.
URI: http://localhost/handle/Hannan/179622
http://localhost/handle/Hannan/647210
ISSN: 1530-4388
1558-2574
volume: 16
issue: 4
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7574298.pdf1.52 MBAdobe PDFThumbnail
Preview File
Title: The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET
Authors: Wen-Kuan Yeh;Wenqi Zhang;Yi-Lin Yang;An-Ni Dai;Kehuey Wu;Tung-Huan Chou;Cheng-Li Lin;Kwang-Jow Gan;Chia-Hung Shih;Po-Ying Chen
subject: FinFET|width quantization|reliability
Year: 2016
Publisher: IEEE
Abstract: In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (W<sub>Fin_bottom</sub>), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner W<sub>Fin_bottom</sub> device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner W<sub>Fin_bottom</sub> device shows more serious degradation on drain current (I<sub>D</sub>) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker W<sub>Fin_bottom</sub> device shows almost insensitively degradation with the variation of stressing voltage.
URI: http://localhost/handle/Hannan/179622
http://localhost/handle/Hannan/647210
ISSN: 1530-4388
1558-2574
volume: 16
issue: 4
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7574298.pdf1.52 MBAdobe PDFThumbnail
Preview File