Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/616864
Full metadata record
DC FieldValueLanguage
dc.contributor.authorManqing Maoen_US
dc.contributor.authorYu Caoen_US
dc.contributor.authorShimeng Yuen_US
dc.contributor.authorChaitali Chakrabartien_US
dc.date.accessioned2020-05-20T09:17:18Z-
dc.date.available2020-05-20T09:17:18Z-
dc.date.issued2016en_US
dc.identifier.issn2156-3357en_US
dc.identifier.issn2156-3365en_US
dc.identifier.other10.1109/JETCAS.2016.2547745en_US
dc.identifier.urihttp://localhost/handle/Hannan/155154en_US
dc.identifier.urihttp://localhost/handle/Hannan/616864-
dc.description.abstractResistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM in main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ReRAM cross-point array. However, 1T1R ReRAM array has significantly lower lifetime compared to a DRAM array. In this paper, we show how cross-layer techniques can be used to improve reliability of 1T1R array with minimum latency and energy cost. At the circuit level, we show how voltage settings (pulse amplitude and pulse width) of word-line (WL), bit-line (BL), and source-line (SL) can be used to lower latency, lower energy consumption and improve reliability. We also show how appropriate choice of voltage settings can help reduce retention and endurance errors while minimizing energy. At the architecture level, we propose a new bit-flipping scheme that helps reduce the Bit Error Rate (BER) even further. We show how application of circuit-level and architecture-level techniques makes it possible to achieve a lifetime of 10 years with a simple BCH (t=2) code. Finally, we evaluate the system-level performances of a 1GB ReRAM and 1GB DRAM memory system using CACTI and GEM5. Simulation results using SPEC CPU INT 2006 and DaCapo-9.12 benchmarks show that the proposed ReRAM based main memory can improve Instruction Per Cycle (IPC) by 5.2% and energy by up to 72% compared to a DRAM memory system.en_US
dc.publisherIEEEen_US
dc.relation.haspart7450693.pdfen_US
dc.subjectretention|reliability|endurance|main memory|energy|1T1R ReRAM|cross-layer technique|latencyen_US
dc.titleOptimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniquesen_US
dc.typeArticleen_US
dc.journal.volume6en_US
dc.journal.issue3en_US
dc.journal.titleIEEE Journal on Emerging and Selected Topics in Circuits and Systemsen_US
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7450693.pdf2.95 MBAdobe PDFThumbnail
Preview File
Full metadata record
DC FieldValueLanguage
dc.contributor.authorManqing Maoen_US
dc.contributor.authorYu Caoen_US
dc.contributor.authorShimeng Yuen_US
dc.contributor.authorChaitali Chakrabartien_US
dc.date.accessioned2020-05-20T09:17:18Z-
dc.date.available2020-05-20T09:17:18Z-
dc.date.issued2016en_US
dc.identifier.issn2156-3357en_US
dc.identifier.issn2156-3365en_US
dc.identifier.other10.1109/JETCAS.2016.2547745en_US
dc.identifier.urihttp://localhost/handle/Hannan/155154en_US
dc.identifier.urihttp://localhost/handle/Hannan/616864-
dc.description.abstractResistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM in main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ReRAM cross-point array. However, 1T1R ReRAM array has significantly lower lifetime compared to a DRAM array. In this paper, we show how cross-layer techniques can be used to improve reliability of 1T1R array with minimum latency and energy cost. At the circuit level, we show how voltage settings (pulse amplitude and pulse width) of word-line (WL), bit-line (BL), and source-line (SL) can be used to lower latency, lower energy consumption and improve reliability. We also show how appropriate choice of voltage settings can help reduce retention and endurance errors while minimizing energy. At the architecture level, we propose a new bit-flipping scheme that helps reduce the Bit Error Rate (BER) even further. We show how application of circuit-level and architecture-level techniques makes it possible to achieve a lifetime of 10 years with a simple BCH (t=2) code. Finally, we evaluate the system-level performances of a 1GB ReRAM and 1GB DRAM memory system using CACTI and GEM5. Simulation results using SPEC CPU INT 2006 and DaCapo-9.12 benchmarks show that the proposed ReRAM based main memory can improve Instruction Per Cycle (IPC) by 5.2% and energy by up to 72% compared to a DRAM memory system.en_US
dc.publisherIEEEen_US
dc.relation.haspart7450693.pdfen_US
dc.subjectretention|reliability|endurance|main memory|energy|1T1R ReRAM|cross-layer technique|latencyen_US
dc.titleOptimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniquesen_US
dc.typeArticleen_US
dc.journal.volume6en_US
dc.journal.issue3en_US
dc.journal.titleIEEE Journal on Emerging and Selected Topics in Circuits and Systemsen_US
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7450693.pdf2.95 MBAdobe PDFThumbnail
Preview File
Full metadata record
DC FieldValueLanguage
dc.contributor.authorManqing Maoen_US
dc.contributor.authorYu Caoen_US
dc.contributor.authorShimeng Yuen_US
dc.contributor.authorChaitali Chakrabartien_US
dc.date.accessioned2020-05-20T09:17:18Z-
dc.date.available2020-05-20T09:17:18Z-
dc.date.issued2016en_US
dc.identifier.issn2156-3357en_US
dc.identifier.issn2156-3365en_US
dc.identifier.other10.1109/JETCAS.2016.2547745en_US
dc.identifier.urihttp://localhost/handle/Hannan/155154en_US
dc.identifier.urihttp://localhost/handle/Hannan/616864-
dc.description.abstractResistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM in main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ReRAM cross-point array. However, 1T1R ReRAM array has significantly lower lifetime compared to a DRAM array. In this paper, we show how cross-layer techniques can be used to improve reliability of 1T1R array with minimum latency and energy cost. At the circuit level, we show how voltage settings (pulse amplitude and pulse width) of word-line (WL), bit-line (BL), and source-line (SL) can be used to lower latency, lower energy consumption and improve reliability. We also show how appropriate choice of voltage settings can help reduce retention and endurance errors while minimizing energy. At the architecture level, we propose a new bit-flipping scheme that helps reduce the Bit Error Rate (BER) even further. We show how application of circuit-level and architecture-level techniques makes it possible to achieve a lifetime of 10 years with a simple BCH (t=2) code. Finally, we evaluate the system-level performances of a 1GB ReRAM and 1GB DRAM memory system using CACTI and GEM5. Simulation results using SPEC CPU INT 2006 and DaCapo-9.12 benchmarks show that the proposed ReRAM based main memory can improve Instruction Per Cycle (IPC) by 5.2% and energy by up to 72% compared to a DRAM memory system.en_US
dc.publisherIEEEen_US
dc.relation.haspart7450693.pdfen_US
dc.subjectretention|reliability|endurance|main memory|energy|1T1R ReRAM|cross-layer technique|latencyen_US
dc.titleOptimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniquesen_US
dc.typeArticleen_US
dc.journal.volume6en_US
dc.journal.issue3en_US
dc.journal.titleIEEE Journal on Emerging and Selected Topics in Circuits and Systemsen_US
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7450693.pdf2.95 MBAdobe PDFThumbnail
Preview File