Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/586938
Title: A Practical Large-Capacity Three-Stage Buffered Clos-Network Switch Architecture
Authors: Yu Xia;Mounir Hamdi;H. Jonathan Chao
subject: packet switch;batch scheduling;Clos network;distributed shared-memory
Year: 2016
Publisher: IEEE
Abstract: This paper proposes a three-stage buffered Clos-network switch (TSBCS) architecture along with a novel batch scheduling (BS) mechanism. We found that TSBCS/BS can be mapped to a “fat” combined input-crosspoint queued (CICQ) switch. Consequently, the well-studied CICQ scheduling algorithms can be directly applied in TSBCS. Moreover, BS drastically reduces the time complexity of TSBCS scheduling when compared with ordinary CICQ switches of the same number of switch ports, which enables us to build a larger-capacity switch with reasonable scheduling complexity. We further show that TSBCS/BS can achieve 100 percent throughput under any admissible traffic if a stable CICQ scheduling algorithm is used. Direct cell forwarding schemes are proposed to overcome the performance drawback of BS under light traffic loads. With extensive simulations, we show that the performance of TSBCS/BS is comparable to that of output-queued switches and the latter are usually considered as theoretical optimal.
Description: 
URI: http://localhost/handle/Hannan/167022
http://localhost/handle/Hannan/586938
ISSN: 1045-9219
volume: 27
issue: 2
Appears in Collections:2016

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Title: A Practical Large-Capacity Three-Stage Buffered Clos-Network Switch Architecture
Authors: Yu Xia;Mounir Hamdi;H. Jonathan Chao
subject: packet switch;batch scheduling;Clos network;distributed shared-memory
Year: 2016
Publisher: IEEE
Abstract: This paper proposes a three-stage buffered Clos-network switch (TSBCS) architecture along with a novel batch scheduling (BS) mechanism. We found that TSBCS/BS can be mapped to a “fat” combined input-crosspoint queued (CICQ) switch. Consequently, the well-studied CICQ scheduling algorithms can be directly applied in TSBCS. Moreover, BS drastically reduces the time complexity of TSBCS scheduling when compared with ordinary CICQ switches of the same number of switch ports, which enables us to build a larger-capacity switch with reasonable scheduling complexity. We further show that TSBCS/BS can achieve 100 percent throughput under any admissible traffic if a stable CICQ scheduling algorithm is used. Direct cell forwarding schemes are proposed to overcome the performance drawback of BS under light traffic loads. With extensive simulations, we show that the performance of TSBCS/BS is comparable to that of output-queued switches and the latter are usually considered as theoretical optimal.
Description: 
URI: http://localhost/handle/Hannan/167022
http://localhost/handle/Hannan/586938
ISSN: 1045-9219
volume: 27
issue: 2
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7054539.pdf1.74 MBAdobe PDFThumbnail
Preview File
Title: A Practical Large-Capacity Three-Stage Buffered Clos-Network Switch Architecture
Authors: Yu Xia;Mounir Hamdi;H. Jonathan Chao
subject: packet switch;batch scheduling;Clos network;distributed shared-memory
Year: 2016
Publisher: IEEE
Abstract: This paper proposes a three-stage buffered Clos-network switch (TSBCS) architecture along with a novel batch scheduling (BS) mechanism. We found that TSBCS/BS can be mapped to a “fat” combined input-crosspoint queued (CICQ) switch. Consequently, the well-studied CICQ scheduling algorithms can be directly applied in TSBCS. Moreover, BS drastically reduces the time complexity of TSBCS scheduling when compared with ordinary CICQ switches of the same number of switch ports, which enables us to build a larger-capacity switch with reasonable scheduling complexity. We further show that TSBCS/BS can achieve 100 percent throughput under any admissible traffic if a stable CICQ scheduling algorithm is used. Direct cell forwarding schemes are proposed to overcome the performance drawback of BS under light traffic loads. With extensive simulations, we show that the performance of TSBCS/BS is comparable to that of output-queued switches and the latter are usually considered as theoretical optimal.
Description: 
URI: http://localhost/handle/Hannan/167022
http://localhost/handle/Hannan/586938
ISSN: 1045-9219
volume: 27
issue: 2
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7054539.pdf1.74 MBAdobe PDFThumbnail
Preview File