Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/218881
Title: Low-latency digit-serial dual basis multiplier for lightweight cryptosystems
Authors: Che Wun Chiou;Chiou-Yng Lee;Jim-Min Lin;Yun-Chi Yeh;Jeng-Shyang Pan
Year: 2017
Publisher: IET
Abstract: Various cryptosystems, such as elliptic curve and pairing-based cryptosystems, in resource-constrained security applications rely on finite field multiplication. For applications such as these, a digit-serial multiplier has the potential features to achieve a trade-off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub-multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub-multiplication units. The proposed architecture uses a four-bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit-serial dual basis multiplier eliminates up to 96% of the critical path delay.
URI: http://localhost/handle/Hannan/218881
volume: 11
issue: 6
More Information: 301,
311
Appears in Collections:2017

Files in This Item:
File SizeFormat 
8089649.pdf2.77 MBAdobe PDF
Title: Low-latency digit-serial dual basis multiplier for lightweight cryptosystems
Authors: Che Wun Chiou;Chiou-Yng Lee;Jim-Min Lin;Yun-Chi Yeh;Jeng-Shyang Pan
Year: 2017
Publisher: IET
Abstract: Various cryptosystems, such as elliptic curve and pairing-based cryptosystems, in resource-constrained security applications rely on finite field multiplication. For applications such as these, a digit-serial multiplier has the potential features to achieve a trade-off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub-multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub-multiplication units. The proposed architecture uses a four-bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit-serial dual basis multiplier eliminates up to 96% of the critical path delay.
URI: http://localhost/handle/Hannan/218881
volume: 11
issue: 6
More Information: 301,
311
Appears in Collections:2017

Files in This Item:
File SizeFormat 
8089649.pdf2.77 MBAdobe PDF
Title: Low-latency digit-serial dual basis multiplier for lightweight cryptosystems
Authors: Che Wun Chiou;Chiou-Yng Lee;Jim-Min Lin;Yun-Chi Yeh;Jeng-Shyang Pan
Year: 2017
Publisher: IET
Abstract: Various cryptosystems, such as elliptic curve and pairing-based cryptosystems, in resource-constrained security applications rely on finite field multiplication. For applications such as these, a digit-serial multiplier has the potential features to achieve a trade-off between space and time complexities. The authors propose an efficient decomposition of the multiplication into four independent sub-multiplication units to facilitate parallel processing, which is additionally facilitated by the systolic structures of the sub-multiplication units. The proposed architecture uses a four-bit scheme to construct a novel processing element, instead of using only one bit as is currently used in similar multipliers. The results of the synthesis show that the proposed digit-serial dual basis multiplier eliminates up to 96% of the critical path delay.
URI: http://localhost/handle/Hannan/218881
volume: 11
issue: 6
More Information: 301,
311
Appears in Collections:2017

Files in This Item:
File SizeFormat 
8089649.pdf2.77 MBAdobe PDF