Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/717058
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dc.contributor.authorMustafa Efendioglu|Alper Sen|Yavuz Korogluen_US
dc.date.accessioned2013en_US
dc.date.accessioned2021-05-16T17:43:46Z-
dc.date.available2021-05-16T17:43:46Z-
dc.date.issueden_US
dc.identifier.isbn0278-0070en_US
dc.identifier.other10.1109/TCAD.2018.2878193en_US
dc.identifier.urihttp://localhost/handle/Hannan/717058-
dc.description.abstractIn system-on-chip design, resources for verification is limited by time-to-market and cost. In order to allocate verification resources effectively, managers need to rely on their experience backed by design related metrics. However, often there are also other aspects of development process, such as bug history and developer information that can improve the effectiveness of verification. Software bug prediction is a machine learning (ML)-based technique which predicts whether a given software module is bug-prone by using product and process metrics of the module. Therefore, it can help direct verification effort, reduce costs, and improve the quality of software. Although there is a plethora of work in software bug prediction, no such work exists for SystemC. We propose an ML-based software bug prediction solution for verification of SystemC models used in virtual prototypes that takes into account system level design metrics and demonstrate its effectiveness on several open source system level designs. We find that 96% of modules could be correctly predicted as buggy or clean.en_US
dc.relation.haspart08509200.pdfen_US
dc.subjectBug prediction|machine learning (ML)|SystemC|verificationen_US
dc.titleBug Prediction of SystemC Models Using Machine Learningen_US
dc.title.alternativeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
dc.typeArticleen_US
dc.journal.volumeVolumeen_US
dc.journal.issueIssueen_US
dc.journal.titleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
Appears in Collections:New Ieee 2019

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Full metadata record
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dc.contributor.authorMustafa Efendioglu|Alper Sen|Yavuz Korogluen_US
dc.date.accessioned2013en_US
dc.date.accessioned2021-05-16T17:43:46Z-
dc.date.available2021-05-16T17:43:46Z-
dc.date.issueden_US
dc.identifier.isbn0278-0070en_US
dc.identifier.other10.1109/TCAD.2018.2878193en_US
dc.identifier.urihttp://localhost/handle/Hannan/717058-
dc.description.abstractIn system-on-chip design, resources for verification is limited by time-to-market and cost. In order to allocate verification resources effectively, managers need to rely on their experience backed by design related metrics. However, often there are also other aspects of development process, such as bug history and developer information that can improve the effectiveness of verification. Software bug prediction is a machine learning (ML)-based technique which predicts whether a given software module is bug-prone by using product and process metrics of the module. Therefore, it can help direct verification effort, reduce costs, and improve the quality of software. Although there is a plethora of work in software bug prediction, no such work exists for SystemC. We propose an ML-based software bug prediction solution for verification of SystemC models used in virtual prototypes that takes into account system level design metrics and demonstrate its effectiveness on several open source system level designs. We find that 96% of modules could be correctly predicted as buggy or clean.en_US
dc.relation.haspart08509200.pdfen_US
dc.subjectBug prediction|machine learning (ML)|SystemC|verificationen_US
dc.titleBug Prediction of SystemC Models Using Machine Learningen_US
dc.title.alternativeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
dc.typeArticleen_US
dc.journal.volumeVolumeen_US
dc.journal.issueIssueen_US
dc.journal.titleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
Appears in Collections:New Ieee 2019

Files in This Item:
File Description SizeFormat 
08509200.pdf1.33 MBAdobe PDFThumbnail
Preview File
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMustafa Efendioglu|Alper Sen|Yavuz Korogluen_US
dc.date.accessioned2013en_US
dc.date.accessioned2021-05-16T17:43:46Z-
dc.date.available2021-05-16T17:43:46Z-
dc.date.issueden_US
dc.identifier.isbn0278-0070en_US
dc.identifier.other10.1109/TCAD.2018.2878193en_US
dc.identifier.urihttp://localhost/handle/Hannan/717058-
dc.description.abstractIn system-on-chip design, resources for verification is limited by time-to-market and cost. In order to allocate verification resources effectively, managers need to rely on their experience backed by design related metrics. However, often there are also other aspects of development process, such as bug history and developer information that can improve the effectiveness of verification. Software bug prediction is a machine learning (ML)-based technique which predicts whether a given software module is bug-prone by using product and process metrics of the module. Therefore, it can help direct verification effort, reduce costs, and improve the quality of software. Although there is a plethora of work in software bug prediction, no such work exists for SystemC. We propose an ML-based software bug prediction solution for verification of SystemC models used in virtual prototypes that takes into account system level design metrics and demonstrate its effectiveness on several open source system level designs. We find that 96% of modules could be correctly predicted as buggy or clean.en_US
dc.relation.haspart08509200.pdfen_US
dc.subjectBug prediction|machine learning (ML)|SystemC|verificationen_US
dc.titleBug Prediction of SystemC Models Using Machine Learningen_US
dc.title.alternativeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
dc.typeArticleen_US
dc.journal.volumeVolumeen_US
dc.journal.issueIssueen_US
dc.journal.titleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
Appears in Collections:New Ieee 2019

Files in This Item:
File Description SizeFormat 
08509200.pdf1.33 MBAdobe PDFThumbnail
Preview File