Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/716988
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dc.contributor.authorMatthew J. Cannon|Andrew M. Keller|Hayden C. Rowberry|Corbin A. Thurlow|Andrés Pérez-Celis|Michael J. Wirthlinen_US
dc.date.accessioned2013en_US
dc.date.accessioned2021-05-16T17:43:32Z-
dc.date.available2021-05-16T17:43:32Z-
dc.date.issueden_US
dc.identifier.isbn0018-9499en_US
dc.identifier.other10.1109/TNS.2018.2877579en_US
dc.identifier.urihttp://localhost/handle/Hannan/716988-
dc.description.abstractTriple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within the configuration memory of static random access memory field-programmable gate arrays. Applying TMR to the design successfully reduces the design's neutron cross section by 80×. The effectiveness of TMR, however, is limited by the presence of single bits in the configuration memory which cause more than one TMR domain to fail simultaneously. We present three strategies to mitigate against these failures and improve the effectiveness of TMR: incremental routing, incremental placement, and striping. These techniques were tested using both fault injection and a wide spectrum neutron beam with the best technique offering a 400× reduction to the design's sensitive neutron cross section. An analysis from the radiation test shows that no single bits caused failure and that multicell upsets were the main cause of failure for these mitigation strategies.en_US
dc.relation.haspart08502717.pdfen_US
dc.subjectsingle-event effects (SEEs)|field programmable gate arrays (FPGAs)|single-event upset (SEU)|triple modular redundancy (TMR)|Configuration scrubbingen_US
dc.titleStrategies for Removing Common Mode Failures From TMR Designs Deployed on SRAM FPGAsen_US
dc.title.alternativeIEEE Transactions on Nuclear Scienceen_US
dc.typeArticleen_US
dc.journal.volumeVolumeen_US
dc.journal.issueIssueen_US
dc.journal.titleIEEE Transactions on Nuclear Scienceen_US
Appears in Collections:New Ieee 2019

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dc.contributor.authorMatthew J. Cannon|Andrew M. Keller|Hayden C. Rowberry|Corbin A. Thurlow|Andrés Pérez-Celis|Michael J. Wirthlinen_US
dc.date.accessioned2013en_US
dc.date.accessioned2021-05-16T17:43:32Z-
dc.date.available2021-05-16T17:43:32Z-
dc.date.issueden_US
dc.identifier.isbn0018-9499en_US
dc.identifier.other10.1109/TNS.2018.2877579en_US
dc.identifier.urihttp://localhost/handle/Hannan/716988-
dc.description.abstractTriple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within the configuration memory of static random access memory field-programmable gate arrays. Applying TMR to the design successfully reduces the design's neutron cross section by 80×. The effectiveness of TMR, however, is limited by the presence of single bits in the configuration memory which cause more than one TMR domain to fail simultaneously. We present three strategies to mitigate against these failures and improve the effectiveness of TMR: incremental routing, incremental placement, and striping. These techniques were tested using both fault injection and a wide spectrum neutron beam with the best technique offering a 400× reduction to the design's sensitive neutron cross section. An analysis from the radiation test shows that no single bits caused failure and that multicell upsets were the main cause of failure for these mitigation strategies.en_US
dc.relation.haspart08502717.pdfen_US
dc.subjectsingle-event effects (SEEs)|field programmable gate arrays (FPGAs)|single-event upset (SEU)|triple modular redundancy (TMR)|Configuration scrubbingen_US
dc.titleStrategies for Removing Common Mode Failures From TMR Designs Deployed on SRAM FPGAsen_US
dc.title.alternativeIEEE Transactions on Nuclear Scienceen_US
dc.typeArticleen_US
dc.journal.volumeVolumeen_US
dc.journal.issueIssueen_US
dc.journal.titleIEEE Transactions on Nuclear Scienceen_US
Appears in Collections:New Ieee 2019

Files in This Item:
File Description SizeFormat 
08502717.pdf1.64 MBAdobe PDFThumbnail
Preview File
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMatthew J. Cannon|Andrew M. Keller|Hayden C. Rowberry|Corbin A. Thurlow|Andrés Pérez-Celis|Michael J. Wirthlinen_US
dc.date.accessioned2013en_US
dc.date.accessioned2021-05-16T17:43:32Z-
dc.date.available2021-05-16T17:43:32Z-
dc.date.issueden_US
dc.identifier.isbn0018-9499en_US
dc.identifier.other10.1109/TNS.2018.2877579en_US
dc.identifier.urihttp://localhost/handle/Hannan/716988-
dc.description.abstractTriple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within the configuration memory of static random access memory field-programmable gate arrays. Applying TMR to the design successfully reduces the design's neutron cross section by 80×. The effectiveness of TMR, however, is limited by the presence of single bits in the configuration memory which cause more than one TMR domain to fail simultaneously. We present three strategies to mitigate against these failures and improve the effectiveness of TMR: incremental routing, incremental placement, and striping. These techniques were tested using both fault injection and a wide spectrum neutron beam with the best technique offering a 400× reduction to the design's sensitive neutron cross section. An analysis from the radiation test shows that no single bits caused failure and that multicell upsets were the main cause of failure for these mitigation strategies.en_US
dc.relation.haspart08502717.pdfen_US
dc.subjectsingle-event effects (SEEs)|field programmable gate arrays (FPGAs)|single-event upset (SEU)|triple modular redundancy (TMR)|Configuration scrubbingen_US
dc.titleStrategies for Removing Common Mode Failures From TMR Designs Deployed on SRAM FPGAsen_US
dc.title.alternativeIEEE Transactions on Nuclear Scienceen_US
dc.typeArticleen_US
dc.journal.volumeVolumeen_US
dc.journal.issueIssueen_US
dc.journal.titleIEEE Transactions on Nuclear Scienceen_US
Appears in Collections:New Ieee 2019

Files in This Item:
File Description SizeFormat 
08502717.pdf1.64 MBAdobe PDFThumbnail
Preview File