Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/631680
Title: Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors
Authors: Junghoon Lee;Taehoon Kim;Jaehyuk Huh
subject: Memory authentication|secure processor architecture|memory organization|cache management|encryption
Year: 2016
Publisher: IEEE
Abstract: To prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor has improved significantly with the counter-mode encryption combined with Bonsai Merkle Tree, our results indicate that multi-core secure processors can suffer from significant performance degradation due to the limited memory bandwidth. To mitigate the performance overheads, this paper proposes three techniques for the multi-core design of secure processors. First, the paper advocates to use a combined cache for all normal and security-supporting data. Second, the paper proposes memory scheduling and mapping schemes for secure processors. Finally, the paper investigates a type-aware cache insertion scheme considering the distinct characteristics of normal and security-supporting data. Our simulation results show that the combined techniques reduce the performance degradation for supporting full confidentiality and integrity, from 25-34 percent to less than 8-14 percent in 8-core and 16-core secure processors, with minimal extra hardware costs.
Description: 
URI: http://localhost/handle/Hannan/159699
http://localhost/handle/Hannan/631680
ISSN: 0018-9340
volume: 65
issue: 11
Appears in Collections:2016

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Title: Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors
Authors: Junghoon Lee;Taehoon Kim;Jaehyuk Huh
subject: Memory authentication|secure processor architecture|memory organization|cache management|encryption
Year: 2016
Publisher: IEEE
Abstract: To prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor has improved significantly with the counter-mode encryption combined with Bonsai Merkle Tree, our results indicate that multi-core secure processors can suffer from significant performance degradation due to the limited memory bandwidth. To mitigate the performance overheads, this paper proposes three techniques for the multi-core design of secure processors. First, the paper advocates to use a combined cache for all normal and security-supporting data. Second, the paper proposes memory scheduling and mapping schemes for secure processors. Finally, the paper investigates a type-aware cache insertion scheme considering the distinct characteristics of normal and security-supporting data. Our simulation results show that the combined techniques reduce the performance degradation for supporting full confidentiality and integrity, from 25-34 percent to less than 8-14 percent in 8-core and 16-core secure processors, with minimal extra hardware costs.
Description: 
URI: http://localhost/handle/Hannan/159699
http://localhost/handle/Hannan/631680
ISSN: 0018-9340
volume: 65
issue: 11
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7425202.pdf1.32 MBAdobe PDFThumbnail
Preview File
Title: Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors
Authors: Junghoon Lee;Taehoon Kim;Jaehyuk Huh
subject: Memory authentication|secure processor architecture|memory organization|cache management|encryption
Year: 2016
Publisher: IEEE
Abstract: To prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor has improved significantly with the counter-mode encryption combined with Bonsai Merkle Tree, our results indicate that multi-core secure processors can suffer from significant performance degradation due to the limited memory bandwidth. To mitigate the performance overheads, this paper proposes three techniques for the multi-core design of secure processors. First, the paper advocates to use a combined cache for all normal and security-supporting data. Second, the paper proposes memory scheduling and mapping schemes for secure processors. Finally, the paper investigates a type-aware cache insertion scheme considering the distinct characteristics of normal and security-supporting data. Our simulation results show that the combined techniques reduce the performance degradation for supporting full confidentiality and integrity, from 25-34 percent to less than 8-14 percent in 8-core and 16-core secure processors, with minimal extra hardware costs.
Description: 
URI: http://localhost/handle/Hannan/159699
http://localhost/handle/Hannan/631680
ISSN: 0018-9340
volume: 65
issue: 11
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7425202.pdf1.32 MBAdobe PDFThumbnail
Preview File