Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/548629
Title: An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture
Authors: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China;Renfeng Dou ; Jun Han ; Yifan Bo ; Zhiyi Yu ; Xiaoyang Zeng
subject: multiplying circuits; multiprocessing systems; network-on-chip; public key cryptography; Montgomery multiplication; RSA; block level parallel algorithm; elliptic curve cryptography; intercore communication latency; modular multiplication; multicore processor; network architecture; network-on-chip; quotient pipelining; task partitioning; Algorithm design and analysis; Broadcasting; Multicore processing; Parallel processing; Partitioning algorithms; Topology; Broadcast; Montgomery multiplication; cryptography; multicast; multicore systems; network-on-chip (NoC); parallel computing; parallel computing.;
Year: 2014
Publisher: IEEE
Abstract: The modular multiplication (MM) is a key operation in cryptographic algorithms, such as RSA and elliptic-curve cryptography. Multicore processor is a suitable platform to implement MM because of its flexibility, high performance, and energy-efficiency. In this paper, we propose a block-level parallel algorithm for MM with quotient pipelining and optimally map it on a network-on-chip-based multicore platform equipped with broadcasting mechanism. Aiming at highest performance, a theoretical speedup model for parallel MM is also developed for parameter exploration that optimizes task partitioning. Experimental results based on a multicore prototype show that compared with the sequential MM on single core, the parallel implementation proposed in this paper maximizes the speedup ratio with regard to given intercore communication latency.
URI: http://localhost/handle/Hannan/282367
http://localhost/handle/Hannan/548629
ISSN: 1063-8210
volume: 22
issue: 11
Appears in Collections:2014

Files in This Item:
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6689343.pdf5.71 MBAdobe PDF
Title: An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture
Authors: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China;Renfeng Dou ; Jun Han ; Yifan Bo ; Zhiyi Yu ; Xiaoyang Zeng
subject: multiplying circuits; multiprocessing systems; network-on-chip; public key cryptography; Montgomery multiplication; RSA; block level parallel algorithm; elliptic curve cryptography; intercore communication latency; modular multiplication; multicore processor; network architecture; network-on-chip; quotient pipelining; task partitioning; Algorithm design and analysis; Broadcasting; Multicore processing; Parallel processing; Partitioning algorithms; Topology; Broadcast; Montgomery multiplication; cryptography; multicast; multicore systems; network-on-chip (NoC); parallel computing; parallel computing.;
Year: 2014
Publisher: IEEE
Abstract: The modular multiplication (MM) is a key operation in cryptographic algorithms, such as RSA and elliptic-curve cryptography. Multicore processor is a suitable platform to implement MM because of its flexibility, high performance, and energy-efficiency. In this paper, we propose a block-level parallel algorithm for MM with quotient pipelining and optimally map it on a network-on-chip-based multicore platform equipped with broadcasting mechanism. Aiming at highest performance, a theoretical speedup model for parallel MM is also developed for parameter exploration that optimizes task partitioning. Experimental results based on a multicore prototype show that compared with the sequential MM on single core, the parallel implementation proposed in this paper maximizes the speedup ratio with regard to given intercore communication latency.
URI: http://localhost/handle/Hannan/282367
http://localhost/handle/Hannan/548629
ISSN: 1063-8210
volume: 22
issue: 11
Appears in Collections:2014

Files in This Item:
File SizeFormat 
6689343.pdf5.71 MBAdobe PDF
Title: An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture
Authors: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China;Renfeng Dou ; Jun Han ; Yifan Bo ; Zhiyi Yu ; Xiaoyang Zeng
subject: multiplying circuits; multiprocessing systems; network-on-chip; public key cryptography; Montgomery multiplication; RSA; block level parallel algorithm; elliptic curve cryptography; intercore communication latency; modular multiplication; multicore processor; network architecture; network-on-chip; quotient pipelining; task partitioning; Algorithm design and analysis; Broadcasting; Multicore processing; Parallel processing; Partitioning algorithms; Topology; Broadcast; Montgomery multiplication; cryptography; multicast; multicore systems; network-on-chip (NoC); parallel computing; parallel computing.;
Year: 2014
Publisher: IEEE
Abstract: The modular multiplication (MM) is a key operation in cryptographic algorithms, such as RSA and elliptic-curve cryptography. Multicore processor is a suitable platform to implement MM because of its flexibility, high performance, and energy-efficiency. In this paper, we propose a block-level parallel algorithm for MM with quotient pipelining and optimally map it on a network-on-chip-based multicore platform equipped with broadcasting mechanism. Aiming at highest performance, a theoretical speedup model for parallel MM is also developed for parameter exploration that optimizes task partitioning. Experimental results based on a multicore prototype show that compared with the sequential MM on single core, the parallel implementation proposed in this paper maximizes the speedup ratio with regard to given intercore communication latency.
URI: http://localhost/handle/Hannan/282367
http://localhost/handle/Hannan/548629
ISSN: 1063-8210
volume: 22
issue: 11
Appears in Collections:2014

Files in This Item:
File SizeFormat 
6689343.pdf5.71 MBAdobe PDF