Please use this identifier to cite or link to this item: http://localhost/handle/Hannan/248122
Title: Techniques for Efficient On-chip Power Delivery and Accurate Leakage Modeling in Nanoscale CMOS
Authors: Jie Gu
Year: 2008
Abstract: Power consumption and process variations are two major issues for the VLSIcircuits with sub-100nm technologies. The soaring of power consumption makespower integrity especially challenging for designers while process variation brings
URI: http://localhost/handle/Hannan/248122
Appears in Collections:Thesis

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TL75578.pdf10.65 MBAdobe PDF
Title: Techniques for Efficient On-chip Power Delivery and Accurate Leakage Modeling in Nanoscale CMOS
Authors: Jie Gu
Year: 2008
Abstract: Power consumption and process variations are two major issues for the VLSIcircuits with sub-100nm technologies. The soaring of power consumption makespower integrity especially challenging for designers while process variation brings
URI: http://localhost/handle/Hannan/248122
Appears in Collections:Thesis

Files in This Item:
File SizeFormat 
TL75578.pdf10.65 MBAdobe PDF
Title: Techniques for Efficient On-chip Power Delivery and Accurate Leakage Modeling in Nanoscale CMOS
Authors: Jie Gu
Year: 2008
Abstract: Power consumption and process variations are two major issues for the VLSIcircuits with sub-100nm technologies. The soaring of power consumption makespower integrity especially challenging for designers while process variation brings
URI: http://localhost/handle/Hannan/248122
Appears in Collections:Thesis

Files in This Item:
File SizeFormat 
TL75578.pdf10.65 MBAdobe PDF