Please use this identifier to cite or link to this item: http://dlib.scu.ac.ir/handle/Hannan/170631
Title: Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning
Authors: Liqun Yang;Haigang Yang;Wei Li;Zhihua Li
subject: semisupervised learning|delay model|MRE|design space exploration|mean relative error|semisupervised model tree|ECOMT|DSE|efficient cotraining model tree|field programmable gate arrays|nonlinear programming|predictive modeling approach|FPGA
Year: 2016
Publisher: IEEE
Abstract: Design space exploration (DSE) is an important step before the physical level design of Field programmable gate arrays (FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture. Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error (MRE) below 5% compared to VTR. Meanwhile the time used to attain the model is less than 3 minutes, which reduces the time of DSE considerably.
URI: http://localhost/handle/Hannan/170631
ISSN: 1022-4653
2075-5597
volume: 25
issue: 1
More Information: 58
63
Appears in Collections:2016

Files in This Item:
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Title: Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning
Authors: Liqun Yang;Haigang Yang;Wei Li;Zhihua Li
subject: semisupervised learning|delay model|MRE|design space exploration|mean relative error|semisupervised model tree|ECOMT|DSE|efficient cotraining model tree|field programmable gate arrays|nonlinear programming|predictive modeling approach|FPGA
Year: 2016
Publisher: IEEE
Abstract: Design space exploration (DSE) is an important step before the physical level design of Field programmable gate arrays (FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture. Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error (MRE) below 5% compared to VTR. Meanwhile the time used to attain the model is less than 3 minutes, which reduces the time of DSE considerably.
URI: http://localhost/handle/Hannan/170631
ISSN: 1022-4653
2075-5597
volume: 25
issue: 1
More Information: 58
63
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7516770.pdf380.46 kBAdobe PDFThumbnail
Preview File
Title: Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning
Authors: Liqun Yang;Haigang Yang;Wei Li;Zhihua Li
subject: semisupervised learning|delay model|MRE|design space exploration|mean relative error|semisupervised model tree|ECOMT|DSE|efficient cotraining model tree|field programmable gate arrays|nonlinear programming|predictive modeling approach|FPGA
Year: 2016
Publisher: IEEE
Abstract: Design space exploration (DSE) is an important step before the physical level design of Field programmable gate arrays (FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture. Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error (MRE) below 5% compared to VTR. Meanwhile the time used to attain the model is less than 3 minutes, which reduces the time of DSE considerably.
URI: http://localhost/handle/Hannan/170631
ISSN: 1022-4653
2075-5597
volume: 25
issue: 1
More Information: 58
63
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7516770.pdf380.46 kBAdobe PDFThumbnail
Preview File