Please use this identifier to cite or link to this item: http://dlib.scu.ac.ir/handle/Hannan/168021
Title: Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
Authors: Jaeduk Han;Yue Lu;Nicholas Sutardja;Kwangmo Jung;Elad Alon
subject: feedforward equalizer (FFE)|current integration|Chip-to-chip communication|high-speed links|decision feedback equalizer (DFE)
Year: 2016
Publisher: IEEE
Abstract: Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies.
URI: http://localhost/handle/Hannan/168021
ISSN: 0018-9200
1558-173X
volume: 51
issue: 4
More Information: 871
880
Appears in Collections:2016

Files in This Item:
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Title: Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
Authors: Jaeduk Han;Yue Lu;Nicholas Sutardja;Kwangmo Jung;Elad Alon
subject: feedforward equalizer (FFE)|current integration|Chip-to-chip communication|high-speed links|decision feedback equalizer (DFE)
Year: 2016
Publisher: IEEE
Abstract: Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies.
URI: http://localhost/handle/Hannan/168021
ISSN: 0018-9200
1558-173X
volume: 51
issue: 4
More Information: 871
880
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7437437.pdf1.65 MBAdobe PDFThumbnail
Preview File
Title: Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
Authors: Jaeduk Han;Yue Lu;Nicholas Sutardja;Kwangmo Jung;Elad Alon
subject: feedforward equalizer (FFE)|current integration|Chip-to-chip communication|high-speed links|decision feedback equalizer (DFE)
Year: 2016
Publisher: IEEE
Abstract: Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies.
URI: http://localhost/handle/Hannan/168021
ISSN: 0018-9200
1558-173X
volume: 51
issue: 4
More Information: 871
880
Appears in Collections:2016

Files in This Item:
File Description SizeFormat 
7437437.pdf1.65 MBAdobe PDFThumbnail
Preview File