مرور بر اساس تاریخ انتشار Sachdev, Manoj

Showing results 1 to 13 of 13
PreviewIssue DateTitleContributor(s)
200832-b ALU in 180-nm CMOS TechnologyChatterjee, Bhaskar; Sachdev, Manoj
2008A comparative analysis of low-power low-voltage dual-edge-triggered flip-flopsChung, Wai; Lo, Timothy; Sachdev, Manoj
2009Design and analysis of A 5.3-pJ 64-kb gated ground SRAM with multiword ECCJahinuzzaman, Shah M.; Shah, Jaspal Singh; Rennie, David J.; Sachdev, Manoj
2008DFT for testing high-performance pipelined circuits with slow-speed testersNummer, Muhammad; Sachdev, Manoj
2008Effect of CMOS technology scaling on thermal management during burn-inSemenov, Oleg; Vassighi, Arman; Sachdev, Manoj; Keshavarzi, Ali; Hawkins, C. F.
2009An Energy Efficient 40 Kb SRAM Module With Extended Read / Write Noise Margin inSharifkhani, Mohammad; Sachdev, Manoj
2013An Energy-Efficient Offset-CancellingShah, Jaspal Singh; Nairn, David; Sachdev, Manoj
2009Low-Leakage Storage Cells for Ternary ContentMohan, Nitin; Sachdev, Manoj
2013A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded MemoryNeale, Adam; Sachdev, Manoj
2011Novel soft error robust flip-flops in 65nm CMOSRennie, David J.; Sachdev, Manoj
2008Segmented virtual ground architecture for low-power embedded SRAMSharifkhani, Mohammad; Sachdev, Manoj
2008Variation-aware adaptive voltage scaling systemElgebaly, Mohamed; Sachdev, Manoj
2008Weak Cell Detection in Deep-Submicron SRAMs : A Programmable Detection TechniquePavlov, Andrei; Sachdev, Manoj